Structure for radio-frequency applications

ABSTRACT

A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.

Notice: This is a reissue application of U.S. Pat. No. 10,347,597 B2,issued Jul. 9, 2019, to Kononchuk et al. for STRUCTURE FORRADIO-FREQUENCY APPLICATIONS.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national phase entry under 35 U.S.C. § 371 ofInternational Patent Application PCT/FR2015/051854, filed Jul. 3, 2015,designating the United States of America and published as InternationalPatent Publication WO 2016/016532 A1 on Feb. 4, 2016, which claims thebenefit under Article 8 of the Patent Cooperation Treaty to FrenchPatent Application Serial No. 14/01800, filed Aug. 1, 2014.

TECHNICAL FIELD

The present application relates to the field of integratedradiofrequency devices.

BACKGROUND

Integrated devices are usually created on substrates in the form ofwafers, which are used mainly as support for the fabrication thereof.However, the increasing degree of integration and the increasingperformance levels expected of these devices is driving an increasinglysignificant coupling between their performance levels and thecharacteristics of the substrate on which they are formed. That isparticularly the case with radiofrequency (RF) devices, processingsignals with a frequency of between approximately 3 kHz and 300 GHz, theapplications of which notably fall within the field oftelecommunications (cellular telephones, WI-FI®, BLUETOOTH®, etc.).

As an example of device/substrate coupling, the electromagnetic fields,deriving from the high-frequency signals propagating in the devices,penetrate into the depth of the substrate and interact with any chargecarriers located therein. This causes problems of nonlinear distortion(harmonics) of the signal, a pointless consumption of a portion of theenergy of the signal by insertion loss and possible influences betweencomponents.

Thus, the RF devices have characteristics governed both by theirarchitecture and their creation processes, and by the capacity of thesubstrate on which they are fabricated to limit the insertion losses,the cross-talks between neighboring devices, and the nonlineardistortion phenomena generating harmonics.

The radiofrequency devices, such as antenna switches, tuners and poweramplifiers, can be created on different types of substrates.

Silicon-on-sapphire substrates are, for example, known, commonly calledSOS (silicon-on-sapphire), which give the components, created accordingto microelectronic technologies in the surface layer of silicon, thebenefit of the insulating properties of the sapphire substrate. Forexample, the antenna switches and power amplifiers fabricated on thistype of substrate exhibit very good figures of merit but are primarilyused for niche applications because of the overall cost of the solution.

Also known are the substrates based on high-resistivity siliconcomprising a support substrate, a trapping layer arranged on the supportsubstrate, a dielectric layer arranged on the trapping layer, and anactive semiconductive layer arranged on the dielectric layer. Thesupport substrate usually exhibits a resistivity higher than 1 k ohm·cm.The trapping layer can comprise non-doped polycrystalline silicon. Thecombination of a high-resistivity support substrate and of a trappinglayer according to the prior art makes it possible to reduce theabove-mentioned device/substrate coupling and thus ensure goodperformance levels in the RF devices. In this respect, a person skilledin the art will find a review of the performance levels of the RFdevices fabricated on the high-resistivity semiconductive substrateknown from the prior art in “Silicon-on-insulator (SOI) Technology,manufacture and applications,” points 10.7 and 10.8, Oleg Kononchuk andBich-Yen Nguyen, from Woodhead Publishing.

Nevertheless, a trapping layer of polysilicon presents the drawback ofundergoing a partial recrystallization in high-temperature heattreatment steps, which contributes to diminishing the trap density inthe layer. With the trend in mobile telephone standards dictatingincreasingly demanding specifications in the RF components, thedegradation of the performance of the device linked to this decrease intrap density is prohibitive for some applications.

Moreover, the step of deposition of the polysilicon and of surfacepreparation in order to produce the stacking of the substrate aresensitive and expensive.

An alternative to this trapping layer of polysilicon is a layer ofporous silicon. A deposition of a porous layer, according to the priorart, does not make it possible to obtain a very thin layer thickness,less than 1 μm. Thus, the porous layers of the prior art and theirthickness, between 10 μm and 80 μm, do not make it possible to obtain asubstrate comprising a porous layer with a mechanical strength that issufficient to withstand certain steps of fabrication of the devices andbe retained in the final functional devices.

BRIEF SUMMARY

An object of the disclosure is, therefore, to propose a structuresuitable for radiofrequency applications, remedying the drawbacks of theprior art. An object of the disclosure is notably to propose anintegrated structure that meets the increasing demands of the RFapplications and that allows for a reduction in fabrication costs.

The disclosure relates to a structure for radiofrequency applicationscomprising:

-   -   a support substrate of high-resistivity silicon comprising a        lower part and an upper part having undergone a p-type doping to        a depth D; and    -   a mesoporous trapping layer of silicon formed in the doped upper        part of the support substrate.

According to the disclosure, the structure is noteworthy in that thedepth D is less than 1 μm and the trapping layer has a porosity rate ofbetween 20% and 60%.

The porosity rate of the trapping layer thus obtained makes it possibleto accurately control its resistivity, at levels that can be high (>5000ohm·cm). Thus, the setting of the porosity rate (according to a preciserange from 20% to 60%) and of the depth D (less than 1 μm) of the dopingof the upper part of the support substrate of silicon in which thetrapping layer will be formed, make it possible:

-   -   to ensure a good mechanical strength of the mesoporous layer,        allowing it to be retained in the final functional device;    -   and to confer properties of resistivity and of insulation on the        structure that are appropriate for radiofrequency applications.

Moreover, the fabrication of a very thin mesoporous trapping layer (lessthan 1 μm) simplifies the step of deposition of the trapping layer onthe support substrate, as well as the potential steps of surfacepreparation necessary for the subsequent process steps to be carriedout.

According to advantageous features of the disclosure, taken alone or incombination:

-   -   the mesoporous trapping layer has pores with a diameter of        between 2 nm and 50 nm;    -   the mesoporous trapping layer is obtained by a process of        electrolysis of the doped upper part of the support substrate;    -   the electrolysis process is controlled by a technique of voltage        control at the terminals of the electrolysis;    -   the resistivity of the lower part of the support substrate is        greater than 1000 ohm·cm.

According to other advantageous features of the disclosure, taken aloneor in combination:

-   -   an active layer is arranged on the trapping layer;    -   the active layer is transferred onto the trapping layer by        direct bonding;    -   the active layer is formed from a semiconductive material;    -   the active layer is formed from a piezoelectric material;    -   the active layer comprises at least one of the materials        selected from the following group: silicon, silicon carbide,        silicon germanium, lithium niobate, lithium tantalate, quartz,        and aluminum nitride;    -   the thickness of the active layer is between 10 nm and 50 μm;    -   a dielectric layer is arranged between the trapping layer and        the active layer;    -   the dielectric layer is transferred onto the trapping layer by        direct bonding;    -   the dielectric layer comprises at least one of the materials        selected from the following group: silicon dioxide, silicon        nitride, and aluminum oxide;    -   the dielectric layer is between 10 nm and 6 μm;    -   a layer of silicon nitride (SiN) is arranged between the        trapping layer and the dielectric layer.

According to other advantageous features of the disclosure, taken aloneor in combination, at least one microelectronic device is present on orin the active layer:

-   -   the microelectronic device is a switching circuit or an antenna        tuning circuit or a radiofrequency power amplification circuit;    -   the microelectronic device comprises a plurality of active        components and a plurality of passive components;    -   the microelectronic device comprises at least one control        element and one MEMS switching element consisting of a        microswitch with ohmic contact or of a capacitive microswitch;    -   the microelectronic device is a radiofrequency filter operating        by bulk or surface acoustic wave propagation.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the disclosure will emerge from thefollowing detailed description with reference to the attached figures inwhich:

FIG. 1 represents the dependency of the Young's modulus with theporosity of the silicon;

FIG. 2 represents a first embodiment of the disclosure;

FIGS. 3A and 3B represent a second embodiment of the disclosure; and

FIG. 4 represents another embodiment of the disclosure.

DETAILED DESCRIPTION

The structure 1, 1′, 11 for radiofrequency applications according to thedisclosure comprises a support substrate 2 of high-resistivity (HR)silicon. High resistivity should be understood to mean a resistivityhigher than 1000 ohm·cm; it is advantageously between 4000 and 10,000ohm·cm.

The support substrate 2 of HR silicon undergoes a p-type doping on anupper part 3 and to a predetermined depth D, less than 1 μm, inaccordance with the disclosure. This doping can advantageously beperformed by ion implantation followed by a bake of RTA type to activatethe implanted p-type dopants, or an epitaxy of a p+ layer, or even adoping by “spin-on-glass” (the term describing a deposition of a layerof glass by centrifugation).

Thus doped, the upper layer part 3 of the support substrate 2″ of HRsilicon is subjected to a process of electrolysis, so as to transformthe upper part 3 of the support substrate 2 into a porous trapping layer4, which will form the trapping layer 4. The depth D of the dopantsintroduced previously into the upper part 3 of the support substrate 2corresponds substantially to the thickness of the trapping layer 4.

The process of electrolysis can consist for example of anelectrochemical anodization, in which at least the upper part 3 of thesupport substrate 2 is placed in a chamber comprising an electrolyte,such as hydrofluoric acid. An anode and a cathode are then dipped intothe electrolyte and powered by a source of electrical current.

There are three types of morphologies for porous silicon:

-   -   macroporous silicon, generally obtained from weakly doped n-type        silicon, and having a pore diameter greater than 50 nm;    -   mesoporous silicon, generally obtained from strongly doped        p-type silicon, and having a pore diameter of between 2 nm and        50 nm;    -   nanoporous (also called microporous) silicon, generally obtained        from weakly doped p-type silicon, and having a pore diameter of        less than 2 nm.

Thus, depending on the level of doping of the support substrate 2 andthe conditions of the electrolysis process, such as the adjustment ofthe electrical current density applied by the source of electricalcurrent, the porosity rate will be higher or lower and controlled. Torecap, the porosity Po of a layer is defined as the fraction of bulkunoccupied within the layer and is expressed as:Po=(d−d_(Po))/dwhere d is the density of the non-porous material and d_(Po) is thedensity of the porous material.

The trapping layer 4 generated has to have a porosity rate that issufficient to obtain a high defect density, suitable for trapping theinversion charges generated in the support substrate 2, and a highresistivity level. However, this porosity rate, coupled with thethickness of the porous trapping layer 4, also characterizes themechanical strength of the trapping layer 4. The dependency of theYoung's modulus (denoted E and expressed in GigaPascal) as a function ofthe porosity rate of the porous layer is represented in FIG. 1 . For agiven thickness, the greater the porosity rate, the lower the mechanicalproperties: the decrease in the Young's modulus as a function of theporosity percentage (Po) reflects this decrease in mechanical strength.Furthermore, for a given porosity rate, the thicker the porous layer,the lower the mechanical properties. The applicant has identified aprocess window for which the porous layer exhibits the mechanicalstrength required to be compatible with subsequent microelectronic steps(deposition, bakes, polishing, etc.), as well as the resistivityproperties required for the radiofrequency applications.

The structure 1, 1′, 11 according to the disclosure, therefore, proposesa trapping layer 4 with a porosity rate that is between 20% and 60% andwith a thickness that is less than 1 μm, so as to ensure mechanical andelectrical performance levels of the structure 1, 1′, 11. The mesoporousmorphology, having pores with a diameter of between 2 nm and 50 nm,makes it possible to achieve the requisite porosity levels, over thethickness of 1 μm, with a significant trap density (typically greaterthan 10¹³/cm², making it possible to trap the inversion charges) and ahigh resistivity.

The thickness D of the trapping layer 4 (of mesoporous silicon) dependson the depth of the p-type doping of the upper part 3 of the supportsubstrate 2. The porosity rate depends on the quantity of dopantsintroduced into the upper part 3 of the support substrate 2 as well asthe electrolysis process performance conditions.

In order to ensure that the porosification by electrolysis of the upperpart 3 of the support substrate 2 does not exceed the predetermineddepth D, a control of the voltage at the terminals of the electrolysisis put in place, making it possible to determine when the porosificationbegins in the non-doped lower part of the support substrate 2 of HRsilicon and, therefore, stop the electrolysis process. Theporosification of the upper part 3 of the support substrate 2 has to bestopped at the end of the diffusion tail of the dopants introduced intothe upper part 3 of the support substrate 2, substantially at the depthD.

The structure 1, 1′, 11 for radiofrequency applications according to thedisclosure thus comprises a trapping layer 4 of mesoporous silicon, theporosity of which is between 20% and 60% and the thickness of which isless than 1 μm, arranged on a support substrate 2 of high-resistivitysilicon. The trapping layer has a typical resistivity greater than 5000ohm·cm.

According to a first embodiment of the disclosure represented in FIG. 2, the structure 1 for radiofrequency applications can take the form of awafer of dimensions compatible with microelectronic processes, forexample, with a diameter of 200 nm or 300 nm, comprising the supportsubstrate 2 and the trapping layer 4 (FIG. 2 , Panel (c)).

The support substrate 2 of HR silicon (FIG. 2 , Panel (a))advantageously has a resistivity greater than 4000 ohm·cm. It first ofall undergoes a boron ion implantation, for example, with a dose of1^(e)13/cm² and with an energy of 50 keV, followed by a heat treatmentat 1000° C. for 5 minutes; a p-doped upper part 3, to a depth ofapproximately 200 nm, is thus created (FIG. 2 , Panel (b)). The supportsubstrate 2 then undergoes an electrolysis: the current density will,for example, be between 10 and 20 mA/cm² and the electrolysis solutionwill have an HF concentration of between 10% and 30%. The mesoporoustrapping layer 4 of silicon is formed in the doped upper part 3 of thesupport substrate 2 (FIG. 2 , Panel (c)). The porosity obtained,dependent on the quantity of dopants and on the current density appliedduring the electrolysis, is of the order of 50%; the pores having a sizeof between 2 and 50 nm. This fabrication process, simple andinexpensive, makes it possible to obtain a structure 1 that exhibitsmechanical and electrical properties compatible with the specificationsof radiofrequency applications:

-   -   a good mechanical strength making it possible to withstand the        various stressful steps of creation of microelectronic        components;    -   stable insulation properties linked to the high resistivity of        the support substrate 2 and to the charge-trapping qualities of        the mesoporous trapping layer 4, even after application of the        high-temperature heat treatments for the creation of        microelectronic components.

A second embodiment of the disclosure is represented in FIG. 3 .According to a first variant of this second embodiment, illustrated inFIG. 3 , Panel (a), the structure 1′ for radiofrequency applications cantake the form of a wafer and further comprise an active layer 5,arranged on the trapping layer 4, in and on which RF components will beable to be created. The active layer 5 will advantageously be able toconsist of semiconductive materials and/or piezoelectric materials.Advantageously, but without this being limiting, the active layer 5comprises at least one of the materials out of: silicon, siliconcarbide, germanium silicon, lithium niobate, lithium tantalate, quartz,aluminum nitride, etc. The thickness of the active layer 5 can vary froma few nanometers (for example, 10 nm) to several tens of microns (forexample, 50 μm) depending on the components to be fabricated.

By way of example, the active layer 5 is transferred onto the supportsubstrate 2 comprising the trapping layer 4, by one of the thin layertransfer processes well known to those skilled in the art, including:

-   -   The SMART CUT® process, based on an implantation of light        hydrogen and/or helium ions in a donor substrate and a bonding,        for example, by molecular adhesion, of this donor substrate        directly onto the trapping layer 4, itself arranged on the        support substrate 2; a detachment step then makes it possible to        separate a thin surface layer from the donor substrate (the        active layer), at the level of the embrittlement plane defined        by the depth of implantation of the ions. Finishing steps, that        can include high-temperature heat treatments, finally confer the        crystalline and surface quality required of the active layer 5.        The process is particularly suited to the fabrication of thin        active layers, with a thickness of between a few nanometers and        approximately 1.5 μm, for example, for layers of silicon.        -   The SMART CUT® process is followed by an epitaxy step,            making it possible, in particular, to obtain thicker active            layers, for example, from a few tens of nm to 20 μm.        -   The direct bonding and mechanical, chemical and/or            mechanical-chemical thinning processes involve assembling a            donor substrate by molecular adhesion directly on the            trapping layer 4, itself arranged on the support substrate            2, then in thinning the donor substrate to the desired            thickness of active layer 5, for example, by grinding and by            polishing (CMP, “chemical mechanical polishing”). These            processes are particularly suited to the transfer of thick            layers, for example, from a few microns to several tens of            microns, and up to a few hundreds of microns.

According to another variant of the second embodiment, represented inFIG. 3 , Panel (b), the structure 1′ for radiofrequency applicationswill also be able to include a dielectric layer 6, arranged between theactive layer 5 and the trapping layer 4. Advantageously, but withoutthis being limiting, the dielectric layer 6 will comprise at least oneof the materials out of: silicon dioxide, silicon nitride, aluminumoxide, etc. Its thickness will be able to vary between 10 nm and 3 μm.

The dielectric layer 6 is obtained by thermal oxidation or by LPCVD orPECVD or HDP deposition, on the trapping layer 4 or on the donorsubstrate prior to the transfer of the active layer 5 onto the trappinglayer 4.

As is well known in the field of SOI (silicon-on-insulator) substratesfor radiofrequency applications, such a dielectric layer, for example,formed by an oxide of silicon on a support substrate of silicon,comprises positive charges. These charges are compensated by negativecharges coming from the support substrate at the interface with thedielectric layer. These charges generate a conduction layer in thesupport substrate, under the dielectric layer, with a resistivity thatdrops around 10-100 ohm·cm. The electrical performance levels sensitiveto the resistivity of the support substrate (such as the linearity ofthe signal, the level of insertion losses, the quality factors of thepassive components, etc.) are, therefore, greatly degraded by thepresence of this conduction layer.

The role of the trapping layer 4 is then to trap all the mobile chargesgenerated in the support substrate 2 in order for it to retain a highand stable resistivity level.

FIG. 4 presents a third embodiment according to the disclosure.According to a first variant of this third embodiment, represented inFIG. 4 , Panel (a), the structure 11 for radiofrequency applications canalso comprise or consist of a microelectronic device 7 on or in theactive layer 5, which is arranged on a dielectric layer 6 or directly onthe trapping layer 4. The microelectronic device 7 can be a switchingcircuit (called “switch”) or an antenna tuning or synchronizationcircuit (called “tuner”) or even a power amplification circuit (called“power amplifier”), created according to silicon microelectronictechnologies. The active layer 5 of silicon typically has a thickness ofbetween 50 nm and 180 nm, for example, 145 nm, and the underlyingdielectric layer 6 has a thickness of between 50 nm and 400 nm, forexample, 200 nm; the trapping layer 4 is arranged between the dielectriclayer 6 and the support substrate 2. The microelectronic device 7created in and on the active layer 5 comprises a plurality of activecomponents (MOS or bipolar type, or the like) and a plurality of passivecomponents (of capacitor, inductor, resistor, resonator, filter type, orthe like).

The fabrication of the microelectronic components entails carrying outseveral steps including high-temperature heat treatments, typically at950° C.-1100° C., or even higher. The trapping layer 4 of mesoporoussilicon described previously retains its physical and electricalproperties after such heat treatments.

According to another variant of this embodiment, represented in FIG. 4 ,Panel (b), the microelectronic device 7 can first of all be created on asubstrate of SOI (silicon-on-insulator) type, then transferred by alayer transfer technique known to those skilled in the art onto astructure 1 according to the disclosure comprising the trapping layer 4arranged on the support substrate 2.

In this particular case, the structure 11 comprises, on the one hand,the support substrate 2 on which the trapping layer 4 is arranged; abovethe latter, there is the layer of components of the microelectronicdevice 7: the so-called “back end” part of metal interconnect anddielectric layers is arranged above the trapping layer 4, the so-called“front end” part (silicon), generated partly in the active layer 5,being itself above the “back end” part. Finally, above, there is theactive layer 5 and, optionally, a dielectric layer 6′.

In these two particular cases, the electromagnetic fields, deriving fromthe high-frequency signals intended to be propagated in themicroelectronic devices 7, and which will penetrate into the trappinglayer 4 and into the support substrate 2, will undergo only low losses(insertion losses) and disturbances (cross-talk, harmonics), because ofthe high and stable resistivity of the support substrate 2 and of thetrapping layer 4. Advantageously, the structure 11 according to thedisclosure benefits from a process of fabrication of the trapping layer4 that is simple and economical compared to the prior art; and it offersat least equivalent performance levels.

According to a fourth embodiment, the structure 11 for radiofrequencyapplications can comprise or consist of a microelectronic device 7comprising at least one control element and one MEMS(microelectromechanical system) switching element consisting of amicroswitch with ohmic contact or of a capacitive microswitch.

The MEMS fabrication can be facilitated by the presence of a dielectriclayer under an active layer of silicon. The structure 11 according tothe disclosure will, therefore, be able to include, by way of example,an active layer 5 of silicon with a thickness of between 20 nm and 2microns, advantageously 145 nm, and an underlying dielectric layer 6with a thickness of between 20 nm and 1 micron, advantageously 400 nm;the trapping layer 4 is arranged between the dielectric layer 6 and thesupport substrate 2. The fabrication of the MEMS part is then based onsurface micromachining techniques, making it possible, in particular, tofree beams or mobile membranes in the active layer of silicon.

Alternatively, the MEMS part can be created directly on the trappinglayer 4, by successive deposition of a plurality of layers (including anelectrode, a dielectric, a sacrificial layer, and an active layer) andby the production of patterns on these different layers.

The microelectronic processes for the fabrication of the controlelement(s) (CMOS, for example), usually performed before the MEMS part,require, as in the preceding embodiment, the application ofhigh-temperature heat treatments. The mechanical strength of thetrapping layer 4 to this type of treatment and its capacity to retainits electrical properties (high resistivity and trap density suitablefor trapping the mobile charges) are, therefore, key advantages.

In the same way as for the third embodiment, the high-frequency signalspropagated in this microelectronic device 7 generate electromagneticfields that penetrate into the trapping layer 4 and into the supportsubstrate 2. The losses (insertion losses), distortions (harmonics) anddisturbances (cross-talk, etc.) will be lesser because of the high andstable resistivity of the support substrate 2 provided with the trappinglayer 4.

According to a fifth embodiment, the structure 11 for radiofrequencyapplications can comprise or consist of a microelectronic device 7comprising a radiofrequency filter operating by bulk acoustic wave (BAW)propagation.

The fabrication of a BAW filter of FBAR (thin-film bulk acousticresonator) type necessitates an active layer 5 consisting of apiezoelectric material, in which the acoustic wave will be containedbetween the two electrodes that surround it. The structure 11 accordingto the disclosure will, therefore, be able to include, by way ofexample, an active layer 5 of aluminum nitride with a thickness ofbetween 50 nm and 1 μm, advantageously 100 nm, and a dielectric layer 6(for example, of silicon oxide) with a thickness of between 1 and 6 μm;the trapping layer 4 is arranged between the dielectric layer 6 and thesupport substrate 2. Insulation cavities are formed under the activelayers of the filter, that is to say, the areas in which the acousticwaves will be required to be propagated.

The fabrication of the BAW filter then entails steps of depositions ofelectrodes to which the RF signal will be applied.

The structure 11 according to the disclosure makes it possible on theone hand to limit the depth of the insulation cavities whose insulationfunction relative to the substrate is made less critical by the high andstable resistivity of the support substrate and of the trapping layer;this is an advantage in terms of simplification, flexibility androbustness in the process of fabrication of these devices. Also, thestructure 11 according to the disclosure makes it possible to obtainbetter performance levels in the filters, notably in terms of linearity.

According to a variant of this fifth embodiment, the microelectronicdevice 7 comprises a radiofrequency filter operating by surface acousticwave (SAW) propagation.

The fabrication of an SAW filter requires an active layer 5 consistingof a piezoelectric material, on the surface of which will be created anelectrode comb: the acoustic wave is intended to be propagated betweenthese electrodes. The structure 11 according to the disclosure will,therefore, be able to include, by way of example, an active layer 5 oflithium tantalate with a thickness of between 200 nm and 20 μm,advantageously 0.6 μm; the trapping layer 4 is arranged between theactive layer 5 and the support substrate 2. A dielectric layer 6 canoptionally be added between the active layer 5 and the trapping layer 4.

The structure 11 according to the disclosure makes it possible to obtainbetter filter performance levels, notably in terms of insertion lossesand of linearity.

The structure 1, 1′, 11 for radiofrequency applications according to thedisclosure is not limited to the embodiments cited above. It is suitedto any application for which high-frequency signals propagate and arelikely to undergo undesirable losses or disturbances in a supportsubstrate, because the physical and electrical characteristics of thetrapping layer 4 arranged on the support substrate 2 confer good RFproperties on the assembly (limiting the losses, nonlinearities andother disturbances).

The invention claimed is:
 1. A structure for radiofrequency applicationscomprising: a support substrate of high-resistivity silicon comprising anon-doped lower part and a p-type doped upper part, the p-typed p-typedoped upper part formed to a depth D of less than 1 micro micron in thesupport substrate; and a mesoporous trapping layer of silicon formed inthe p-type doped upper part of the support substrate, the mesoporoustrapping layer having a porosity rate of between 20% and 60% such thatthe mesoporous trapping layer traps inversion charges susceptible to begenerated in the non-doped lower part and the non-doped lower partretains a high and stable resistivity level.
 2. The structure of claim1, wherein the mesoporous trapping layer has pores with a diameter ofbetween 2 nm and 50 nm.
 3. The structure of claim 2, wherein theresistivity of the non-doped lower part of the support substrate isgreater than 1000 ohm·cm.
 4. The structure of claim 1, wherein an activelayer is disposed over the mesoporous trapping layer.
 5. The structureof claim 4, wherein the active layer compromises comprises asemiconductive material.
 6. The structure of claim 4, wherein the activelayer compromises comprises a piezoelectric material.
 7. The structureof claim 4, wherein the active layer comprises at least one materialselected from the group consisting of: silicon, silicon carbide, silicongermanium, lithium niobate, lithium tantalate, quartz, and aluminumnitride.
 8. The structure of claim 4, wherein the a thickness of theactive layer is between 10 nm and 50 μm.
 9. The structure of claim 4,wherein a dielectric layer is disposed between the mesoporous trappinglayer and the active layer.
 10. The structure of claim 9, wherein thedielectric layer comprises at least one material selected from the groupconsisting of: silicon dioxide, silicon nitride, and aluminum oxide. 11.The structure of claim 10, wherein the dielectric layer is between 10 nmand 6 μm.
 12. The structure of claim 4, wherein at least onemicroelectronic device is present on or in the active layer, themicroelectronic device being a switching circuit or an antenna tuningcircuit or a radiofrequency power amplification circuit.
 13. Thestructure of claim 4, wherein at least one microelectronic device ispresent on or in the active layer, the microelectronic device comprisinga plurality of active components and a plurality of passive components.14. The structure of claim 4, wherein at least one microelectronicdevice is present on or in the active layer, the microelectronic devicecomprising at least one control element and one MEMS switching elementcomprising a microswitch with ohmic contact or a capacitive microswitch.15. The structure of claim 4, wherein at least one microelectronicdevice is present on or in the active layer, the microelectronic devicecomprising a radiofrequency filter operating by bulk or surface acousticwave propagation.
 16. The structure of claim 1, wherein the resistivityof the non-doped lower part of the support substrate is greater than1000 ohm·cm.
 17. The structure of claim 1, wherein an active layer isarranged disposed on the mesoporous trapping layer.
 18. The structure ofclaim 9, wherein the dielectric layer is between 10 nm and 6 μm.
 19. Asurface acoustic wave device, comprising: a support substrate ofhigh-resistivity silicon comprising a lower portion and an upperportion, wherein silicon in the upper portion of the support substratehas been modified to form a charge trapping layer; a piezoelectricmaterial bonded over a top surface of the support substrate, and havinga thickness between 10 nm and 50 microns; and an electrode comb disposedon a surface of the piezoelectric material; wherein the charge trappinglayer traps mobile charges generated in the upper portion of the supportsubstrate in order to maintain a high and stable resistivity level inthe upper portion of the support substrate.
 20. The surface acousticwave device of claim 19, wherein the piezoelectric material comprises atleast one material selected from the group consisting of: silicon,silicon carbide, silicon germanium, lithium niobate, lithium tantalate,quartz, and aluminum nitride.
 21. The surface acoustic wave device ofclaim 20, wherein the piezoelectric material is lithium tantalate. 22.The surface acoustic wave device of claim 21, wherein the lithiumtantalate has a thickness between 200 nm and 20 μm.
 23. The surfaceacoustic wave device of claim 19, wherein the charge trapping layer hasa thickness below 1 μm.
 24. The surface acoustic wave device of claim19, wherein the charge trapping layer comprises high-resistivity siliconhaving p-type doping.
 25. The surface acoustic wave device of claim 19,wherein the charge trapping layer comprises high-resistivity siliconhaving a porous layer.
 26. The surface acoustic wave device of claim 25,wherein the porous layer comprises pores having a pore diameter lessthan 50 nm.
 27. The surface acoustic wave device of claim 25, whereinthe porous layer comprises pores having a pore diameter between 2 nm and50 nm.
 28. The surface acoustic wave device of claim 25, wherein theporous layer comprises pores having a pore diameter greater than 2 nm.29. The surface acoustic wave device of claim 19, wherein at least onemicroelectronic device is present on or in the piezoelectric material.30. The surface acoustic wave device of claim 29, wherein the at leastone microelectronic device comprises at least one component selectedfrom the group consisting of: a switching circuit, an antenna tuningcircuit, and a radiofrequency power amplification circuit.
 31. Thesurface acoustic wave device of claim 19, further comprising adielectric disposed between the piezoelectric material and the chargetrapping layer.
 32. The surface acoustic wave device of claim 31,wherein the dielectric comprises silicon oxide.
 33. The surface acousticwave device of claim 19, wherein a resistivity of the support substrateis greater than 4000 ohm-cm.
 34. A surface acoustic wave device,comprising: a high-resistivity silicon support substrate; a chargetrapping material disposed on the support substrate; a dielectricmaterial disposed on the charge trapping material; a piezoelectricmaterial disposed on the dielectric material and having a thicknessbetween 10 nm and 50 microns; and electrode comb elements configured topropagate an acoustic wave between them, and disposed on a surface ofthe piezoelectric material; wherein the charge trapping layer isconfigured to trap mobile charges generated in a portion of the supportsubstrate during operation of the surface acoustic wave device.
 35. Thesurface acoustic wave device of claim 34, wherein the piezoelectricmaterial is lithium tantalate.
 36. The surface acoustic wave device ofclaim 34, wherein the dielectric material has a thickness between 10 nmand 6 μm.
 37. A method of manufacturing a surface acoustic wave device,comprising: providing a support substrate; modifying a top portion ofthe support substrate to form a charge trapping layer, the chargetrapping layer configured to trap mobile charges generated in a portionof the support substrate during operation of the surface acoustic wavedevice; disposing a dielectric layer on the charge trapping layer;direct bonding a piezoelectric layer on the dielectric layer bydisposing a donor substrate by molecular adhesion directly on the chargetrapping layer, and thinning the donor substrate to a desired thicknessof the piezoelectric layer of between 10 nm and 50 microns; anddisposing an electrode comb on a surface of the piezoelectric material.38. The method of claim 37, wherein direct bonding the piezoelectriclayer on the dielectric layer comprises direct bonding lithium tantalateon the dielectric layer.
 39. The method of claim 38, wherein directbonding the lithium tantalate on the dielectric layer comprises directbonding the lithium tantalate at a thickness between 200 nm and 20 μm onthe dielectric layer.
 40. The method of claim 37, wherein modifying thetop portion of the support substrate to form the charge trapping layercomprises rendering the top portion of the support substrate a porouslayer.
 41. The method of claim 40, wherein rendering the top portion ofthe support substrate the porous layer comprises forming pores having apore diameter between 2 nm and 50 nm.
 42. The method of claim 37,wherein the dielectric layer comprises at least one material selectedfrom the group consisting of: silicon dioxide, silicon nitride, andaluminum oxide.
 43. The method of claim 37, wherein the dielectric layeris between 10 nm and 6 μm.
 44. The method of claim 37, furthercomprising disposing another dielectric layer on the piezoelectric layerbefore direct bonding the piezoelectric layer on the dielectric layer.